Minimizing peak current in combinational circuit test

Minimizing Power Dissipation in Combinational Circuits During Test Application

Yield, Reliability and Power Supply considerations motivate the need to minimize power dissipation during test application. Two techniques for minimizing power dissipation when tests are applied to static CMOS combinational circuits are proposed. They are: (i) Test set ordering; and (ii) Repetition of test vectors. We show that: although (i) is NP-Hard good heuristics can be developed; and an o...

Combinational Circuit Concurrent Test Generation: A Brief Overview

The complexity of VLSI devices increases rapidly as technology increases, resulting in an increase in the difficulty of test generation. Traditional test generation algorithms target one fault of a fault set at a time to generate a test. This paper presents a brief overview of a few different approaches to concurrent test generation. Concurrent test generation is the process of generating tests...

Estimation of Peak Current through CMOS VLSI Circuit Supply Lines

|We present a new approach for estimating the maximum instantaneous current through the power supply lines of CMOS VLSI circuits. Our nal goal is to determine the peak currents and voltage drops through power supply lines of real VLSI circuits within a practical time. Our approach is based on the iMax algorithm[1] of estimating the upper bound of the current, and uses an improved timed ATPG-bas...

Difference between combinational circuit and sequential circuit pdf

IR-drop Reduction Through Combinational Circuit Partitioning

IR-drop problem is becoming more and more important. Previous works dealing with power/ground (P/G) network peak current reduction to reduce the IR-drop problem only focus on synchronous sequential logic circuits which consider the combinational parts as unchangeable [4],[5]. However, some large combinational circuits which work alone in one clock cycle can create large current peaks and induce...